Please refer to FIG. 1, a block diagram illustrating a conventional single port static random access memory (SRAM) cell. The 6T SRAM (6 transistor static random access memory) cell includes four transistors PU1, PU2, PD1 and PD2 to constitute a latch circuit 10 and the other two transistors PG1 and PG2 to serve as a switch circuit 11. The latch circuit 10 includes two inverter circuits 101 and 102, each of which consists of two transistors. A peripheral read/write circuit (not shown) applied in the SRAM cell performs read/write operations to the SRAM cell and other SRAM cells (not shown) in the same row through the same word line WL.
Please refer to FIG. 2A, a voltage waveform chart for a successful write operation to the SRAM cell of FIG. 1. The voltage level at the left node VL is logic high “1” and the voltage level at the right node VR is logic low “0” prior to a write cycle TWL. During the write cycle TWL, the peripheral read/write circuit pulls the voltage VBL of the left bit line BL down to the ground voltage GND and pulls the voltage VBLB of the right bit line BLB up to the power voltage VDD. The bit lines BL and BLB are complementary bit lines. Meanwhile, the transistors PG1 and PG2 of the switch circuit 11 are switched on in response to a high logic state of a control signal on the word line WL. Therefore, the left node VL is discharged from the logic high level to a lower voltage until VL is low enough to change the output voltage VR of the right inverter circuit 102 consisting of the transistors PU2 and PD2 from logic low “0” to logic high “1”. On the other hand, the right node VR is charged from the logic low level to a higher voltage until VR is high enough to change the output voltage VL of the left inverter circuit 101 consisting of the transistors PU1 and PD1 from logic high “1” to logic low “0”.
Please refer to FIG. 2B, a voltage waveform chart of a write operation failure to the SRAM cell of FIG. 1. As described above, the voltage level at the left node VL is logic high “1” and the voltage level at the right node VR is logic low “0” prior to a write cycle TWL. During the write cycle TWL, the peripheral read/write circuit pulls the voltage VBL of the left bit line BL down to the ground voltage GND and pulls the voltage VBLB of the right bit line BLB up to the power voltage VDD. The bit lines BL and BLB carry complementary signals. Meanwhile, the transistor PG1 and PG2 of the switch circuit 11 are switched on in response to the high logic state of the control signal on the word line WL. Therefore, the left node VL is discharged from the logic high level and the right node VR is charged from the logic low level. However, for some reasons, the discharge and charge rates decrease. It is shown that till the end of the write cycle TWL, the left node VL can not reach the low voltage threshold required to successfully change the output voltage of the right inverter circuit 102 from logic low “0” to logic high “1”. Similarly, the right node YR can not reach the high voltage threshold required to successfully change the output voltage of the left inverter circuit 101 from logic high “1” to logic low “0”. Thus, the write operation to the SRAM cell fails. To ensure successful data write operation to the SRAM cell, one method is applied to prolong the write cycle TWL. Unfortunately, a longer duration of the write cycle TWL results in increased power consumption, and thus it is disadvantageous to applications of portable electronic devices.
Several methods have been proposed to solve the aforementioned problem, e.g. “A 40 nm 1.0 Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control”, Wei-Nan Liao et al., 2013 IEEE 26th International SOC Conference (SOCC 2013), pp. 110-115, “A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit”, Keiichi Kushida et al., 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 25-28 and the related U.S. Pat. No. 8451672. However, there are still other drawbacks. Liao's disclosure only tracks the voltage pull-down in the memory cell, but does not ensure whether the data write operation to the memory cell is successful or not. Thus, the problem about write operation failure is not entirely overcome. Kushida's disclosure cannot adaptively adjust the supply voltage to the memory cell for purpose of reduction of overall power consumption. Nevertheless, the adaptive adjustment is not applicable to various memory cells with process variation.
Therefore, it is desired to provide a memory write tracking device and a memory write tracking method capable of adaptively determining an optimum write cycle TWL for various memory cells so as to effectively ensure successful write operation to the memory cells.